1. Field of the Invention
The present invention relates to a parallel data path architecture suitable for a pseudo-SRAM and, more particularly, to an architecture that permits reading data from a memory array in a number of different operating modes and clock frequencies.
2. Description of the Related Art
Static random access memory (SRAM) chips have commonly been employed in mobile and wireless devices such as wireless telephones. Unlike dynamic random access memory (DRAM) devices, SRAMs retain information in a memory array while power remains applied without need of periodic refresh operations. While having advantages such as speed, cost, and ease of operation, SRAMs are considerably bulkier than DRAMs of a comparable memory capacity, since each storage element (memory cell) of an SRAM memory array requires more transistors than a DRAM storage element. Read and write operations in SRAMs in mobile applications have typically been performed asynchronously (i.e., without use of a clock signal) using a signal data rate (SDR) mode (i.e., one bit is accessed with each column access pulse. By contrast, DRAMs are generally operated synchronously, using an externally supplied clock to carry out read and write operations with an SDR interface or a double date rate (DDR) interface, wherein two bits are accessed with each clock pulse, one on the rising edge and one on the falling edge.
As more features and functions have been incorporated into wireless telephones, such as digital cameras, speech processing, games, ring tones, etc., increased memory requirements have made conventional SRAMs less desirable due to size considerations. Consequently, pseudo-SRAMs are now being used in mobile applications such as wireless telephones. As is known in the art, pseudo-SRAMs are actually DRAM devices that essentially mimic the operation of SRAM devices. Like other DRAM devices, pseudo-SRAMs require a periodic refresh operation to maintain data in the memory cell array, although the refresh operation is hidden from the controller. On a DRAM, the data path is the portion of the chip that controls data flow and timing during read and write operations. During the write operation, the data path transfers data from the chip pads to the memory array where the data is stored. During a read operation, the data path brings the data out of the memory array and onto the pads so that the data can be driven off the chip to another device via a bus or the like.
The architecture and design of the data path is affected by the DRAM interface, its operating mode, and the clock frequency at which the chip is operating. Since pseudo-SRAM chips are being more widely used, for compatibility with a variety of systems and devices, it would be desirable for pseudo-SRAM chips to include an asynchronous interface of earlier SRAM chips and the synchronous interface of current commodity DRAMs. In the case of synchronous operation, such pseudo-SRAMs should be capable of operating over a wide range of clock frequencies and data latencies.